Engineering Blog

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity gray1_tb is end gray1_tb; architecture TB of gray1_tb is   signal clk    : std_logic := '0';   signal rst    : std_logic := '0';   signal output : std_logic_vector(3 downto 0); begin   UUT : entity work.gray1           port map (               clk    => clk,               rst    => rst,               output => output); clk <= not clk after 10 ns; process begin   rst <= '1';   for i in 0 to 3 loop       wait until rising_edge(clk);   end loop;   rst <= '0';   wait until rising_edge(clk);   wait; end process; end TB;

;********************************************** ;3/1/2019 ;Transmitts strings of characters from uP to PC ;********************************************** .include "ATxmega128A1Udef.inc" .dseg .org 0x2000 Outs:  .BYTE 3 .cseg .org 0x0000 rjmp Main Main: ldi YL, low(Outs) ;input ldi YH, high(Outs) ldi XL, low(Outs) ;output ldi XH, high(Outs) ldi r16, 0xFF ;echo test sts PORTC_DIR, r16 sts PORTC_OUT, r16 rcall USART_INIT ;setup USART rcall IN_STRING rcall OUT_STRING LOOP: rjmp LOOP ;****************************************** ;This subroutine initializes the USART ;frame = 8 stop = 1 parity = odd ;baud = 115200 USART = PORT D ;****************************************** USART_INIT: push r16 ;push reg used ldi r16, 0x08 ;Rx out, rest in sts PORTD_DIRSET, r16 ldi r16, 0x18 ;Tx and Rx enables sts USARTD0_CTRLB, r16 ldi r16, 0x33 ;00 - async, 11 - odd sts USARTD0_CTRLC, r16 ;0 -

--Simple ALU library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity alu_ns is generic( WIDTH : positive := 16 ); port ( input1 : in std_logic_vector(WIDTH-1 downto 0); input2 : in std_logic_vector(WIDTH-1 downto 0); sel : in std_logic_vector(3 downto 0); output : out std_logic_vector(WIDTH-1 downto 0); overflow : out std_logic ); end alu_ns; architecture ALU of alu_ns is begin process(input1, input2, sel) variable temp_mult : unsigned(2*width downto 0); variable temp : unsigned(width downto 0); begin --output <= (others => '0'); overflow <= '0'; case sel is when "0000" => temp := unsigned(input1) + unsigned(input2); overflow <= temp(width); when "0001" => temp := unsigned(input1) - unsigned(input2); when "0010" => temp_mult := unsigned(input1) * unsigned(input2); temp := temp_mult(width-1 downto 0); if (temp_m

;**********************************************  ;3/13/2019 ;Blink LED  ;**********************************************  .include "ATxmega128A1Udef.inc" .equ BIT0 = 0x01 .org 0x0 rjmp MAIN MAIN: ldi R16, BIT0 sts PORTC_DIRSET, R16 sts PORTA_DIRCLR, R16 sts PORTC_OUT, R16 POLLING: lds R16, PORTA_IN andi r16, BIT0 cpi r16, BIT0 brne POLLING ldi r19, 0x01 rcall DELAY_X_10MS sts PORTC_OUTTGL, R16 rjmp POLLING ;******************************************  ;Delays by x10 ms  ;****************************************** DELAY_X_10MS:  cpi r19, 0 ;5 passed in from LOOP  brne LOOP3 ;if not 0, go again  ret  LOOP3:  rcall DELAY_10MS  dec r19  brne LOOP3  ret  ;******************************************  ;delays by 10 ms  ;******************************************  DELAY_10MS:  ldi r17, 0x16 ;outer loop @ 1B LOOP1:  dec r17  brne START_COUNT  ret START_COUNT:  ;ldi r18,