Engineering Blog

 I have recently started a new role as a test engineer for Blue Origin, very very excited! :)  Here is a little video of one of the projects:

  Created the Developmental Flight Instrumentation (DFI) Checkout Tool for Avionics. Worked as both a Avionics console engineer (sat launch count down for Artemis I), and hardware instrumentation engineer for the DFI installation and testing.  Thank you NASA & TOSC for a good run :) 

My current posting: Project Artemis -- leads to NASA YouTube video

function song = playSong(theVoices) fs = 8000; spp = 0.2;    %a zero vector with respect to the final pulse position and duration song = zeros(1, 321*spp*fs);    %cycling thought the different voices f or ii = 1:length(theVoices)        %cycling through each voice to build the song     for kk = 1:length(theVoices(ii).noteNumbers)        note = real(0.1*exp(1j*2*pi*(440*2^((theVoices(ii).noteNumbers(kk)- 49)/12))*((1/fs):(1/fs):            (theVoices(ii).durations(kk)*spp))));      %start and end pulses with regards to fs locstart = theVoices(ii).startPulses(kk)*1600;      locend = locstart + length(note) - 1;      song(locstart:locend) = song(locstart:locend) + note;    end end load 'handel.mat'; filename = 'lab3song5.wav'; soundsc(song, fs); audiowrite(filename, song, 8000); OUTPUT

TOP library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use work.MIPS_LIB.all; entity Mips is port (         clk             : in std_logic;         rst             : in std_logic;                sw_inport_data : in std_logic_vector(8 downto 0);          sw_inport_sel  : in std_logic;          sw_inport_wr   : in std_logic;   outport: out std_logic_vector(31 downto 0)      ); end Mips; architecture logic of Mips is    signal  PC_write   :   std_logic;    signal  I_or_D      :   std_logic;    signal  mem_write  :   std_logic;    signal mem_read    :   std_logic;    signal mem_reg   :   std_logic;    signal ir_write    :   std_logic;    signal is_signed  :   std_logic;    signal reg_write   :   std_logic;    signal jmp_link:   std_logic;    signal  reg_dst    :   std_logic;    signal alu_A    :   std_logic;    signal alu_B    :   std_logic_vector(1 downto 0);    signal PC_src      :   std_lo

Night at the Engineering Lab  final game demo Narrated by: William Dao