Engineering Blog

My current posting: Project Artemis -- leads to NASA YouTube video

function song = playSong(theVoices) fs = 8000; spp = 0.2;    %a zero vector with respect to the final pulse position and duration song = zeros(1, 321*spp*fs);    %cycling thought the different voices f or ii = 1:length(theVoices)        %cycling through each voice to build the song     for kk = 1:length(theVoices(ii).noteNumbers)        note = real(0.1*exp(1j*2*pi*(440*2^((theVoices(ii).noteNumbers(kk)- 49)/12))*((1/fs):(1/fs):            (theVoices(ii).durations(kk)*spp))));      %start and end pulses with regards to fs locstart = theVoices(ii).startPulses(kk)*1600;      locend = locstart + length(note) - 1;      song(locstart:locend) = song(locstart:locend) + note;    end end load 'handel.mat'; filename = 'lab3song5.wav'; soundsc(song, fs); audiowrite(filename, song, 8000); OUTPUT

TOP library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use work.MIPS_LIB.all; entity Mips is port (         clk             : in std_logic;         rst             : in std_logic;                sw_inport_data : in std_logic_vector(8 downto 0);          sw_inport_sel  : in std_logic;          sw_inport_wr   : in std_logic;   outport: out std_logic_vector(31 downto 0)      ); end Mips; architecture logic of Mips is    signal  PC_write   :   std_logic;    signal  I_or_D      :   std_logic;    signal  mem_write  :   std_logic;    signal mem_read    :   std_logic;    signal mem_reg   :   std_logic;    signal ir_write    :   std_logic;    signal is_signed  :   std_logic;    signal reg_write   :   std_logic;    signal jmp_link:   std_logic;    signal  reg_dst    :   std_logic;    signal alu_A    :   std_logic;    signal alu_B    :   std_logic_vector(1 downto 0);    signal PC_src      :   std_lo

Night at the Engineering Lab  final game demo Narrated by: William Dao

#include <iostream> #include <thread> #include <unistd.h> #include <stdio.h> #include <stdlib.h> #include <future> #include <functional> void bar(std::future<int>& fut){ //get the promised variable //allocate memory for buffer int len = fut.get(); //get variable char * buff; //create buffer buff = (char*) malloc (len+1); //allocate memory if(buff==NULL){ //exit if no allocation exit(1); } for(int n=0;n<len;n++){ buff[n]=rand()%26+'a'; } buff[len]='\0'; std::cout<<"\nvalue: "<<buff<<'\n'; free(buff); //free memory } void foo(){ //get integer        //create promise //engage future //send future to new thread std::promise<int> malin; //create promise std::future<int> fut = malin.get_future(); //engage, make it so! std::thread th1 (bar, std::ref(fut)); //send future to thread int i,n; std::

/************************************** 3/28/2019 ADC for CdS photocell and user input  that provides voltage readings via UART ***************************************/ /***************INCLUDES***************/ #include <avr/io.h> #include <avr/interrupt.h> /***********INITIALIZATIONS************/ int16_t result; volatile  adc_conv_rdy = 0; uint8_t  low_byte; uint8_t  high_byte; #define LETTER 0x41 #define ZERO 0x30 #define CR 0x0D #define LF 0x0A #define ONE 0x31 #define TWO 0X32 /************FUNCTIONS*****************/ void adc_init(void); void tcc0_init(void); void usartd0_init(void); void usart_d0_out_char(char c); void output_voltage(int16_t result); /***************MAIN*******************/ int main(void){ tcc0_init(); adc_init(); usartd0_init(); PMIC.CTRL = PMIC_HILVLEN_bm; //enable sei(); while(1){ if( adc_conv_rdy=1 ) { //check if ready adc_conv_rdy=0; usart_d0_out_char(low_byte);

UNDERWATER SCENE

COMPUTER ROOM HALLWAY STORAGE ROOM CLASS ROOM

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity gray1_tb is end gray1_tb; architecture TB of gray1_tb is   signal clk    : std_logic := '0';   signal rst    : std_logic := '0';   signal output : std_logic_vector(3 downto 0); begin   UUT : entity work.gray1           port map (               clk    => clk,               rst    => rst,               output => output); clk <= not clk after 10 ns; process begin   rst <= '1';   for i in 0 to 3 loop       wait until rising_edge(clk);   end loop;   rst <= '0';   wait until rising_edge(clk);   wait; end process; end TB;

;********************************************** ;3/1/2019 ;Transmitts strings of characters from uP to PC ;********************************************** .include "ATxmega128A1Udef.inc" .dseg .org 0x2000 Outs:  .BYTE 3 .cseg .org 0x0000 rjmp Main Main: ldi YL, low(Outs) ;input ldi YH, high(Outs) ldi XL, low(Outs) ;output ldi XH, high(Outs) ldi r16, 0xFF ;echo test sts PORTC_DIR, r16 sts PORTC_OUT, r16 rcall USART_INIT ;setup USART rcall IN_STRING rcall OUT_STRING LOOP: rjmp LOOP ;****************************************** ;This subroutine initializes the USART ;frame = 8 stop = 1 parity = odd ;baud = 115200 USART = PORT D ;****************************************** USART_INIT: push r16 ;push reg used ldi r16, 0x08 ;Rx out, rest in sts PORTD_DIRSET, r16 ldi r16, 0x18 ;Tx and Rx enables sts USARTD0_CTRLB, r16 ldi r16, 0x33 ;00 - async, 11 - odd sts USARTD0_CTRLC, r16 ;0 -

--Simple ALU library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity alu_ns is generic( WIDTH : positive := 16 ); port ( input1 : in std_logic_vector(WIDTH-1 downto 0); input2 : in std_logic_vector(WIDTH-1 downto 0); sel : in std_logic_vector(3 downto 0); output : out std_logic_vector(WIDTH-1 downto 0); overflow : out std_logic ); end alu_ns; architecture ALU of alu_ns is begin process(input1, input2, sel) variable temp_mult : unsigned(2*width downto 0); variable temp : unsigned(width downto 0); begin --output <= (others => '0'); overflow <= '0'; case sel is when "0000" => temp := unsigned(input1) + unsigned(input2); overflow <= temp(width); when "0001" => temp := unsigned(input1) - unsigned(input2); when "0010" => temp_mult := unsigned(input1) * unsigned(input2); temp := temp_mult(width-1 downto 0); if (temp_m

;**********************************************  ;3/13/2019 ;Blink LED  ;**********************************************  .include "ATxmega128A1Udef.inc" .equ BIT0 = 0x01 .org 0x0 rjmp MAIN MAIN: ldi R16, BIT0 sts PORTC_DIRSET, R16 sts PORTA_DIRCLR, R16 sts PORTC_OUT, R16 POLLING: lds R16, PORTA_IN andi r16, BIT0 cpi r16, BIT0 brne POLLING ldi r19, 0x01 rcall DELAY_X_10MS sts PORTC_OUTTGL, R16 rjmp POLLING ;******************************************  ;Delays by x10 ms  ;****************************************** DELAY_X_10MS:  cpi r19, 0 ;5 passed in from LOOP  brne LOOP3 ;if not 0, go again  ret  LOOP3:  rcall DELAY_10MS  dec r19  brne LOOP3  ret  ;******************************************  ;delays by 10 ms  ;******************************************  DELAY_10MS:  ldi r17, 0x16 ;outer loop @ 1B LOOP1:  dec r17  brne START_COUNT  ret START_COUNT:  ;ldi r18,